1. Field of the Invention
The present invention relates to a method for testing a Read Only Memory (hereinafter called “ROM”) and a test circuit therefor.
2. Description of the Related Art
FIG. 5 is a circuit diagram showing one example of a conventional ROM test method. FIG. 6 is a time chart showing a procedure for testing ROMs using a circuit shown in FIG. 5. In the conventional example, CS_1 corresponding to a chip select signal for a ROM1 and OE_1 for enabling an output gate are first made effective. All address spaces of the ROM1 are accessed and data thereof are outputted to their corresponding terminals and then compared with expected values, whereby the ROM1 is checked. Thereafter, a similar test was repeated to carry out tests on a ROM2 and a ROM3.
A patent document 1 (see Japanese Unexamined Patent Publication No. Hei 8(1996)-184645) discloses another test method wherein in a semiconductor integrated circuit with a plurality of ROMs built therein, data read from a plurality of ROM blocks corresponding to address data inputted thereto are subjected to addition or subtraction respectively, and the results thereof are outputted to output terminals via buffers and compared with expected values, thereby checking for ROM data.
In the conventional test method shown in FIGS. 5 and 6, however, a test time increases in proportion to the number of the mounted ROMs, thus leading to an increase in manufacturing cost. Since the method described in the patent document 1 is a method of performing addition or subtraction on the data outputted from the plurality of ROMs and checking the results thereof against the expected values, the result of addition or subtraction might coincide with the expected value even when an error occurs in some of the data. Therefore, the present method was accompanied by a drawback that the error in ROM data could not be checked properly.